“The Advanced Patterning Tool-Box for Continued Semiconductor Scaling” by Chris Bencher, Applied Materials, Inc.

WHEN:
September 11, 2012 3:30 pm - September 11, 2012 4:30 pm
WHERE:
CPE 2.218
Phone: 512-471-5238
200 E. Dean Keeton St., Austin, TX, United States, 78705 Google Map

Chris Bencher, Applied Materials, Inc.

Seminar Abstract:

EUV lithography, for patterning semiconductors, has made tremendous technical progress in recent years; however on a commercial cost basis, it is still years away from displacing immersion lithography combined with various integration tricks such as double exposure or sidewall spacer double patterning.  Sidewall spacer double patterning, for example, has enabled accelerated scaling of NAND-Flash thru three generation of shrink beyond the capabilities of conventional immersion lithography.  In this talk, we will review many of these double, and even quadruple patterning integrations schemes, which is not just useful for extending immersion lithography, but will ultimately be combined with EUV lithography to reach even smaller sub-resolution features.

 

Bio:

Chris Bencher is a Distinguished Member of the Technical Staff working in the CTO office of Applied Materials on path-finding and commercialization of Advanced Patterning Techniques.  Throughout his 15 year term at Applied, Chris has conducted research and development in lithography films, double patterning and triple patterning integration schemes, and recently directed self-assembly.  For the last 5 years, Chris has been a leading advocate for Sidewall Spacer Double Patterning, which has now been adopted by all NAND-Flash manufacturers.  Recent collaborations with the designers and EDA community have helped to prepare the spacer patterning infrastructure for more complex patterns in logic microprocessors.  Before joining the semi-conductor industry in the early 90′s, Chris graduated from Rensselaer and UC Berkeley with degrees in Materials Science.

iCal Import + Google Calendar